1 00:00:00,180 --> 00:00:06,920 So system generator also rich on some implementation of Digital Signal Processing libraries 2 00:00:07,050 --> 00:00:09,260 and some DSP functions there. 3 00:00:09,570 --> 00:00:17,040 So we can process our audio/video or multimedia with those digital signal processing library 4 00:00:17,040 --> 00:00:28,080 and we can even utilized this DSP functions; for DSP block for like communication and other projects and we can 5 00:00:29,190 --> 00:00:35,060 automatically generate the hardware description language that is VHDL/Verilog from that System Generator 6 00:00:35,060 --> 00:00:35,360 -Sys. Gen. 7 00:00:35,370 --> 00:00:44,580 And this system generator is available at Simulink ontalking about MATLAB/Simulink, so we can go 8 00:00:44,580 --> 00:00:56,100 to the traditional Simulink Design and design our projects but we need to have some opening; 9 00:00:56,100 --> 00:01:02,170 We need to open Systems Generator interface from our FPGA design tool installation. 10 00:01:02,190 --> 00:01:11,860 So if you go to the program list on the Start menu of Xilinx and there is a icon called Systems Generator. So 11 00:01:11,930 --> 00:01:20,900 Systems Generator is the interface between traditional FPGA design tool and Simulink so we can so utilize some verified blocks (model) 12 00:01:21,090 --> 00:01:27,160 or blocks of Simulink for Systems Generator and later on we can include Systems Generator icon in the design and we can generate 13 00:01:27,670 --> 00:01:35,530 HDL and we can implement that Systems Generator project directly to the hardware that is FPGA and we can simulate that design which 14 00:01:35,620 --> 00:01:40,550 we are going to talk in another presentations/slides. 15 00:01:40,570 --> 00:01:42,320 So as we talk recently; 16 00:01:42,340 --> 00:01:45,710 So if you want to configure your Systems Generator which we also talk in, 17 00:01:45,890 --> 00:01:46,770 previous section; 18 00:01:46,900 --> 00:01:50,940 But we will /let's resume it and you can go to these type of icons. 19 00:01:51,010 --> 00:02:00,690 Actually we are talking about Windows 7 environment operating systems, so you can; you can go to a Systems Generator 20 00:02:00,690 --> 00:02:09,510 MATLAB configuration inside that Xilinx installation on Start Menu and you can go to 21 00:02:10,560 --> 00:02:16,650 configure the Systems Generator which we have already talked on previous section and you can open that Systems Generator 22 00:02:16,650 --> 00:02:19,720 from this icon; that is second icon; that is Systems Generator. 23 00:02:19,740 --> 00:02:27,360 So if you click this Systems Generator then it would automatically open the MATLAB for Systems Generator 24 00:02:27,390 --> 00:02:28,320 interface. 25 00:02:28,320 --> 00:02:36,450 So here we have VIVADO environment in Windows and ISE environment; ISE Design Tool environment 26 00:02:36,460 --> 00:02:43,460 in Windows. So, both have similar type interface for Systems Generator and so we can configure our Systems Generator 27 00:02:43,500 --> 00:02:44,420 from VIVADO Design Tool or 28 00:02:44,510 --> 00:02:54,510 ISE ; from any of this one. So, and on talking about System Generator based design flow actually on each design 29 00:02:54,580 --> 00:03:03,480 flow, we can; we need to insert these type of icon in our design block design so we can design 30 00:03:04,470 --> 00:03:12,360 our block/model; or we can have block design in the System Generator and we can generate as HDL from that Block/Model. 31 00:03:12,720 --> 00:03:21,580 So System Generator provides us interface provides us facility or features for generating the 32 00:03:21,600 --> 00:03:22,160 HDL-Hardware Description Language. 33 00:03:22,350 --> 00:03:30,240 And we can synthesize that HDL implemented it and upload it to the FPGA in traditional manner or we can even 34 00:03:31,260 --> 00:03:40,070 directly go to System Verification, so we can run our generated HDL directly into Hardware from that System Generator 35 00:03:40,080 --> 00:03:49,050 Option. And we can simulate the; or Run the co-simulation from that System Generator and we can even do the 36 00:03:49,180 --> 00:03:56,550 Functional Simulation, timing simulation.Actually the yellow part is based upon System Generator and other 37 00:03:56,570 --> 00:04:00,730 white part is based on traditional FPGA design tool that is ISE or VIVADO. 38 00:04:00,990 --> 00:04:07,150 So we can export out HDL to ISE/VIVADO and synthesize it implement it and download on hardware/FPGA. Or we can 39 00:04:07,330 --> 00:04:17,160 directly goto system verification, from that System Generator it automatically allow us to the System Verification Option. 40 00:04:17,160 --> 00:04:18,050 And another design flow is, 41 00:04:18,690 --> 00:04:21,430 We can even do the functional simulation from that System Generator. 42 00:04:21,530 --> 00:04:25,410 And other white parts on the figure are for traditional FPGA Design Tool. 43 00:04:25,630 --> 00:04:33,420 We can see; we can create our black blocks in Simulink or System Generator interface that we can create our block building 44 00:04:33,420 --> 00:04:40,400 block as other blocks in System Generator and we can also include these type of ModelSim block for that 45 00:04:40,410 --> 00:04:48,980 we need to install some ModelSim for System Generator and we can do the hardware Co-simulation like we can see here. 46 00:04:49,680 --> 00:04:58,210 And if you want to implement on hardware then there would be two options; one we can do that to process from System Generator, 47 00:04:58,250 --> 00:05:06,350 or we can export our HDL from System Generator to traditional FPGA Design Tool (Xilinx ISE/VIVADO). 48 00:05:06,570 --> 00:05:09,920 And Second flow is again here, 49 00:05:09,940 --> 00:05:17,650 So we can go to HDL generator we can Synthesize the design and it can completely be drawn from System Generator 50 00:05:17,660 --> 00:05:24,380 option or we can export that HDL to Traditional FPGA Design tool- ISE/VIVADO design which we are talking on. 51 00:05:24,540 --> 00:05:28,080 So for creating System Generator based design. 52 00:05:28,080 --> 00:05:35,190 So what we can do it we can open our System Generator from the Start Menu of your Operating System inside the 53 00:05:35,240 --> 00:05:37,940 start menu and inside it 54 00:05:37,950 --> 00:05:46,350 there will have some ISE/VIVADO program list and you can go to System Generator and open the System Generator 55 00:05:46,360 --> 00:05:53,970 and if you click on System Generator it will open the this type of options or menu then you can create a new block design 56 00:05:54,010 --> 00:05:54,430 option and 57 00:05:54,750 --> 00:06:03,680 you can just select block of System Generator and import that block on your current design so you can 58 00:06:03,680 --> 00:06:11,240 customize it and you can integrate it with all other building blocks from the block design option on 59 00:06:11,240 --> 00:06:15,330 System Generator and you can select and search different types of block there. 60 00:06:15,370 --> 00:06:21,290 and first time if you are configuring your System Generator then it will take 61 00:06:21,500 --> 00:06:29,750 little bit more time for synchronizing all the building blocks for System Generator from Simulink & ISE.And, after you did the 62 00:06:29,750 --> 00:06:36,900 project first time then in the next times or in the next projects it will do much faster 63 00:06:37,250 --> 00:06:44,940 on Searching and importing those block from ISE & System Generator library and we can see there like basic elements as Counter, 64 00:06:45,010 --> 00:06:48,070 and delays like block are there and for communication 65 00:06:48,140 --> 00:06:54,350 There are some error correction block and M code block and black blocks are in control logic. We can see FFT & FIR 66 00:06:54,510 --> 00:07:01,130 and FDA tool.Actually , we are going to utilize this DSP building block on System Generator later.So, there are 67 00:07:01,130 --> 00:07:08,300 FDA tool FFT & FIR building blocks which we are going to utilize on upcoming projects and there 68 00:07:08,300 --> 00:07:16,380 are different xilinx blocks in index and mathematical blocks, accumulate blocks in math, like math section. In memory 69 00:07:16,590 --> 00:07:25,070 there is a dual port RAM, Single Port RAM. In tools there is Resource Estimator,ModelSim,WaveScope etc. 70 00:07:25,620 --> 00:07:33,460 and on talking about this all Xilinx blocks inside that all Xilinx Blocks there is block called System Generator (icon). 71 00:07:33,530 --> 00:07:36,610 So we need to have that System Generator Icon on 72 00:07:36,890 --> 00:07:46,780 Every project which are targeted to implement an FPGA. so for talking about Configuration of each block, so here we have 73 00:07:46,860 --> 00:07:47,750 examples of 74 00:07:47,770 --> 00:07:55,550 FIR compiler 5.0 , this is Xilinx FIR compiler blocks so we can customize this block as our requirements. 75 00:07:55,550 --> 00:07:58,830 so we need to just double click on this type of Block/IP. 76 00:07:58,850 --> 00:08:05,780 So if we don't click on this IP then what happens is, we can see the type of option there, so we can configure our 77 00:08:06,790 --> 00:08:15,290 variables there. so we can see Arithmetic type and it takes Unsigned or 2's compliment of values in arithmetic 78 00:08:15,290 --> 00:08:24,000 type and we can go too or we can customize implement with Xilinx Smart IP Core, actually these are the 79 00:08:24,000 --> 00:08:28,710 general customization options which will not available in each block 80 00:08:28,730 --> 00:08:32,400 But most of the block have this type of options. 81 00:08:32,610 --> 00:08:40,040 So, we can set up latency, we can set up some overflow and quantisation, we can override with doubles, 82 00:08:40,080 --> 00:08:49,410 we can have and we can set a precision and some sample period for like FFT and IFFT or FIR and IIR Filter 83 00:08:49,580 --> 00:09:00,800 block. So,we can set up the parameters and here we have Number Format in System Generator actually FPGA are 84 00:09:00,890 --> 00:09:09,280 good for Fixed Point Computations. so if we want to process some Floating point data then we 85 00:09:09,280 --> 00:09:11,360 can Offload or 86 00:09:11,360 --> 00:09:17,260 we can process those data on processor and if we want the process Floating Point data with FPGA? 87 00:09:17,460 --> 00:09:23,090 Then we need to convert it into Fixed Point format or it will automatically utilize Fixed Point library. 88 00:09:23,090 --> 00:09:33,160 So here we have some Fixed Point representation so we can see Xilinx Blockset's uses n bit Fixed Point numbers. 89 00:09:33,260 --> 00:09:38,870 so that Fixed Point number is 2's complement of or two's complement is optional there. 90 00:09:39,050 --> 00:09:47,150 So it's actully obtain the Fixed Point value from the floating point so it converts automatically into fixpoint 91 00:09:49,320 --> 00:09:51,170 Signed o Un-signed. 92 00:09:51,530 --> 00:09:55,140 So we're going to talk about this "Number System" in 93 00:09:55,310 --> 00:10:03,690 upcoming lab also and we're going to go to "Gateway in out block" so that block is available at Xilinx Blockset's, 94 00:10:03,870 --> 00:10:07,300 MATLAB I/O and Gateway In/Out. 95 00:10:07,550 --> 00:10:19,760 So this block actually used for that Floating Point to Fixed Point Conversion, Fixed Point precision so we can provide normal output 96 00:10:19,760 --> 00:10:30,320 to this Gateway In/Out block and it will convert that normal input to Fixed Point Precision data. 97 00:10:30,380 --> 00:10:34,750 So, we can setup the sample period for some time of or for some type of like processing block 98 00:10:35,060 --> 00:10:38,430 like FIR , IIR block. 99 00:10:38,570 --> 00:10:46,080 So, we need to setup our some frequency; some sample period for processing audio and 100 00:10:46,080 --> 00:10:56,680 multimedia and we can set up sample period as 44100. So, that means it will be executed every 44100 101 00:10:56,680 --> 00:11:06,570 times per second so we can also remember the Nyquist theorem. So, it shows that 102 00:11:06,570 --> 00:11:09,840 Sampling frequency must be 2 times of Maximum frequency. 103 00:11:10,050 --> 00:11:14,000 So this is taken at sampling frequency, 104 00:11:14,010 --> 00:11:15,700 That is 44100. 105 00:11:15,930 --> 00:11:28,640 That is one by 44100 is that is the period of; one of the block functions operation per second. 106 00:11:28,880 --> 00:11:33,300 This is the System Generator token so this System Generator token is actually needed for 107 00:11:33,330 --> 00:11:36,750 each and every System Generator block design. 108 00:11:36,750 --> 00:11:40,910 So if we don't include this then that (HDL generation/Co-Simulation) will not work for us. 109 00:11:41,160 --> 00:11:49,090 So this icon only provides us some options for FPGA design, offloading FPGA or targeting FPGA design 110 00:11:49,110 --> 00:11:50,310 options from here. 111 00:11:50,310 --> 00:11:55,450 So we can even convert HDL from our System Generator block design, Block Design into HDL 112 00:11:55,680 --> 00:11:56,480 from this icon. 113 00:11:56,640 --> 00:12:01,780 So this provides some HDL netlist generation option and Bitstream generation option and run 114 00:12:01,780 --> 00:12:02,730 Co-stimulation option 115 00:12:02,790 --> 00:12:06,900 So this block is heavily important for us. 116 00:12:07,030 --> 00:12:13,640 So inside that if we double click on that block, we can see this type of options or this type of functions there. 117 00:12:13,970 --> 00:12:20,100 so we can check the Compilation as Netlist and we can select the part and we can select the Synthesize tool 118 00:12:20,130 --> 00:12:26,430 And we can select the Hardware description language which are going to Output, targeted directory, project type etc. 119 00:12:26,970 --> 00:12:35,610 And we can see here the clocking features here so we can set up the clock, FPGA clock & location 120 00:12:35,610 --> 00:12:37,330 also. 121 00:12:38,080 --> 00:12:41,800 Until this System Generator actually we just have talked about MATLAB/Simulink & System Generator. 122 00:12:42,000 --> 00:12:50,160 So, MATLAB/Simulink provides System Generator interface for Xilinx ISE or VIVADO. 123 00:12:50,230 --> 00:12:54,380 So let's talk a little bit about Xilinx ISE & VIVADO. So, ISE design suit 124 00:12:54,400 --> 00:12:57,850 can import that System Generator exported design, 125 00:12:57,870 --> 00:13:04,800 That HDL design and utilized that design for synthesizing ,implementing and generating it can again 126 00:13:04,830 --> 00:13:07,000 program the FPGA. 127 00:13:07,260 --> 00:13:08,690 And ISE Design Suit, 128 00:13:08,820 --> 00:13:12,100 We already know about this tool/things actually provide a System Generator interface for us. 129 00:13:15,360 --> 00:13:22,630 System Generator also provide some interface/ basic graphical user interface of ISE design suit. On talking about 130 00:13:22,630 --> 00:13:30,570 Xilinx FPGA programming with HDL Coder, actually HDL Coder is another part so it actually provides us some functions 131 00:13:30,570 --> 00:13:39,390 ,some functions means we can convert our design into HDL format by directly using HDL coder compiler. 132 00:13:39,470 --> 00:13:47,370 It also can convert normal MATLAB projects into HDL format and so we can 133 00:13:50,250 --> 00:13:53,090 utilize that HDL in ISE or in VIVADO Design Suit and 134 00:13:53,090 --> 00:13:59,160 used that HDL for traditional design flow that is synthesizing, implementing 135 00:13:59,160 --> 00:14:00,590 and generating Bitstream. 136 00:14:00,840 --> 00:14:09,240 So this HDL coder is important for conversion of MATLAB algorithms and even Simulink models 137 00:14:09,370 --> 00:14:18,090 into HDL format and actually System Generator also provide some extra features like generating Bitstream implementing hardware 138 00:14:18,440 --> 00:14:19,230 Co-Simulation. 139 00:14:19,290 --> 00:14:28,020 And HDL coder can only do that is conversion of HDL from that MATLAB algorith and simulink Model's. So, 140 00:14:28,080 --> 00:14:34,050 HDL coder is just a converter and System Generator is actually not only the converter, System Generator also provide 141 00:14:34,050 --> 00:14:43,620 some implementation, Co-simulation and like Bitstream generation option there. So, here we can see generation 142 00:14:43,630 --> 00:14:44,700 of HDL source code. 143 00:14:44,700 --> 00:14:53,080 So after we implement the MATLAB algorithms so we can utilize that HDL coder and convert that MATLAB algorithm into 144 00:14:53,090 --> 00:14:56,030 RTL(Register Transfer Language) or HDL format. 145 00:14:56,370 --> 00:15:04,830 And we can talk about "Program Xilinx FPGA using HDL Coder with Xilinx System Generator" so we already talk about 146 00:15:04,830 --> 00:15:13,470 System Generator. Actually, System Generator provide us generation of Hardware description anguage based netlist 147 00:15:13,590 --> 00:15:23,440 implementing directly on FPGA, running co-simulation & generating the project like options/features and we have 148 00:15:23,480 --> 00:15:31,550 "Program Xilinx Zynq SoC devices with Embedded Coder & HDL coder". Actually there is also program called embedded coder 149 00:15:31,550 --> 00:15:33,270 that is necessary for programming that processing system in Zynq FPGA. 150 00:15:33,320 --> 00:15:43,350 So Zynq FPGA can be programmed by HDL coder for programmable logic (PL) & embedded coder for 151 00:15:43,550 --> 00:15:47,000 processing system(PS). So, this features will also talk on a later session. 152 00:15:47,000 --> 00:15:55,520 So we have some basic explanation of all these features actually Zynq uses; Zynq 7000 is the 7 series of FPGA from Xilinx. 153 00:15:55,520 --> 00:16:04,090 so it uses AXI interface for communication between traditional programmable logic and ARM 154 00:16:04,280 --> 00:16:06,620 processor inside that Zynq 7000. 155 00:16:06,620 --> 00:16:14,060 So we need to program FPGA that is programmablel logic with the HDL coder based designs and embedded coder 156 00:16:14,060 --> 00:16:14,360 based 157 00:16:14,360 --> 00:16:21,410 design need to uploading into ARM processing core that is processing system core. 158 00:16:21,830 --> 00:16:24,060 So we need to know about two things. 159 00:16:24,060 --> 00:16:28,980 So we already talk: HDL coder is necessary for Programmable Logic, while both 160 00:16:29,260 --> 00:16:32,020 HDL & Embedded coder are necessary for Zynq based design. 161 00:16:32,060 --> 00:16:35,870 So HDL coder is really good for traditional FPGA design. 162 00:16:35,890 --> 00:16:36,260 While, 163 00:16:36,440 --> 00:16:44,810 If you want to or if you want program Microblaze or Processing system or ARM processor inside that FPGA then 164 00:16:44,850 --> 00:16:52,040 we need to have in that Embedded Coder. So, we can see the design flow here so embedded coder targeted for ARM 165 00:16:52,040 --> 00:16:52,830 processor inside that Xilinx Zynq. 166 00:16:52,910 --> 00:16:56,630 and HDL coder is targeted for FPGA core that is Programmable Logic inside that Zynq. 167 00:16:57,100 --> 00:17:00,770 So we can Run our project. 168 00:17:02,060 --> 00:17:08,660 So both things are integrated inside that template and it'll be uploaded to FPGA from that 169 00:17:08,780 --> 00:17:11,650 MATLAB/Simulink interface. 170 00:17:11,690 --> 00:17:17,080 So another thing we have talked about HDL verifier actually HDL verifier provides some design and 171 00:17:17,080 --> 00:17:24,450 verification option's so we can simulate our design and we can run our FPGA design in 172 00:17:24,450 --> 00:17:30,630 Hardware in Loop option so we can verify our design and we can also integrate some Modelsim/Cadence 173 00:17:31,460 --> 00:17:39,330 and QuastaSim simulator inside that MATLAB/Simulink .so that HDL verifier allows us to create testbench and run the simulation. 174 00:17:40,040 --> 00:17:41,340 So HDL verifier design flow can be seen here, 175 00:17:41,500 --> 00:17:43,630 so MATLAB/Simulink is there 176 00:17:44,030 --> 00:17:49,340 And we can design on MATLAB/Simulink based project that is MATLAB based algorithms and Simulink based 177 00:17:49,580 --> 00:17:54,000 model designs and we can use HDL Verifier for Co-Simulation and FPGA in loop. 178 00:17:54,010 --> 00:18:03,290 So if we use FPGA in loop then it will go to FPGA and it will again provide feedback to HDL verifer i.e MATLAB based 179 00:18:04,260 --> 00:18:04,730 interface. 180 00:18:05,060 --> 00:18:13,020 And if we run the Co-Simulation then it also again run the simulator and updates the result in HDL verifier. 181 00:18:13,190 --> 00:18:18,980 So here are some references, actually there are some user guides like UG897 which is VIVADO system generator user guide. 182 00:18:18,980 --> 00:18:25,440 and there are some references for MATLAB that is mathworks.com 183 00:18:25,560 --> 00:18:27,310 and xilinx.com 184 00:18:27,350 --> 00:18:29,060 So you can review those links. 185 00:18:29,120 --> 00:18:37,310 So guys we would have Lab session in an upcoming video lecture so we'll continue on in another video. 186 00:18:37,550 --> 00:18:37,950 Thank You Guys!