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So let's try to focus on profiling in this specific section, right, so we'll be considering how you

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do a profiling with any say timer with the 64 bit global timer that we have.

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And the last thing that we've been doing is the in-built profiling feature that we have with and why

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you decided, right?

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So for our first case, when we discuss how we do profiling, get an excited Daimler mate.

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So first thing that we need to do is to include any, say, timer IP that is mandatory there if you

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plan to perform profiling with any exciting merit.

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So let's first start all the mandatory rules, which allow us to interface the exact time where IP with

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the processing system, right?

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So we go to a useful configuration in the general tab.

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We enable the clock reset.

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Then we go to GP Mastery Ixi interface, and we'll enable Mexi to be zero interface.

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OK, we go to a clock configuration and will allow people fabric, let it just use an output frequency

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or 100 megahertz rate.

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So this will be the frequency that will be used for a profile.

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So we will be later understanding how we use this frequency rate.

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So here we choose how to make our time.

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Click OK.

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So now we have all the necessary board that allow us to interface our exciting IP with the zinc processing

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system so we know at any time great a.

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So we just acquired a single 32 bit timer, right?

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So it will just be reconfiguring our essay time or AP, OK, to include only a single timer to be.

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I'm checking this and click, OK, right?

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So this is done.

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We perform a collection automation that allow us to automatically connect essay time where IP to housing

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processing system.

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Right?

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So now you will see we have a zinc processing system, and it's a time where IP which are connected

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together with the help of any exchange token.

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Great.

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We do not want any of the output from desi excited.

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So we will just be keeping on the plane's loading.

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OK.

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So this basically retreated into only two ports, which are present in our design, right?

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So we have a DDR fixed view.

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With this, we see to perform a validation of design.

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So once validation is successful, we proceed and create, and I still have all the pools which are

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present in our design already have the respect to hard work and.

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So we can directly proceed for termination of a bitstream as soon as I wrap, it is ready.

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Right?

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So our rapid is ready.

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We proceed to do the best you.
