1 00:00:00,540 --> 00:00:07,320 You are saying is the next step is to perform a validation of this and to what validation of design 2 00:00:07,320 --> 00:00:13,200 do is it would check whether all the mandatory collection required for all the peripherals are met or 3 00:00:13,200 --> 00:00:13,430 not. 4 00:00:13,510 --> 00:00:13,650 Right. 5 00:00:13,650 --> 00:00:17,730 So we'll just be clicking on validation of our design excellence. 6 00:00:17,730 --> 00:00:19,080 Validation is successful. 7 00:00:19,160 --> 00:00:21,540 OK, so we could proceed for generation of us. 8 00:00:22,140 --> 00:00:24,090 So here we have our bureaucracy. 9 00:00:24,390 --> 00:00:29,010 We go to a small step over here and you could see we have our doctors and we're here. 10 00:00:29,010 --> 00:00:35,190 So just right click on the blog U.S. and select Create Right and then you get two options. 11 00:00:35,280 --> 00:00:38,770 But we will allow be wide open indeed the wrapper for us. 12 00:00:39,000 --> 00:00:42,090 So just keep the default option and hit on the right. 13 00:00:42,300 --> 00:00:48,240 So once Soul School is ready right now, you could see the Flow Navigator light, so flow. 14 00:00:48,240 --> 00:00:53,430 Navigate it, highlight the different steps that we perform in an FPGA design for right. 15 00:00:53,430 --> 00:00:59,760 So we perform a simulation analysis and synthesis implementation and finally reach an Databricks room, 16 00:01:00,030 --> 00:01:01,800 followed by programming and FPGA. 17 00:01:01,840 --> 00:01:07,770 Right now, you will see we have a two intermediate step, so synthesis is one of an intermediate step 18 00:01:08,430 --> 00:01:10,140 and then generation of objects. 19 00:01:10,740 --> 00:01:11,070 OK. 20 00:01:11,400 --> 00:01:16,860 So when you perform synthesis this assume that you have your two points which are present, right? 21 00:01:16,860 --> 00:01:21,440 So we have a DDA and Fixé, which is present in our design right now. 22 00:01:21,450 --> 00:01:28,080 If your design consists of a food which are not connected to any given week, then you need to perform 23 00:01:28,080 --> 00:01:34,770 the synthesis first before proceeding to generation or else if you are, all the polls which are presenting 24 00:01:34,780 --> 00:01:38,060 their design are all really connected to the respective FPGA. 25 00:01:38,240 --> 00:01:42,210 And then you could just go ahead and start generation of qubits virtual. 26 00:01:42,420 --> 00:01:47,490 All the intermediate steps will be automatically performed and then assuming we can do so, next question 27 00:01:47,490 --> 00:01:53,460 is how you know that all the pools which are present in the design are connected to the respective pins? 28 00:01:53,820 --> 00:01:54,080 Right. 29 00:01:54,150 --> 00:01:55,860 So we have two methods to do that. 30 00:01:55,920 --> 00:02:00,930 So the simplest method that we have with us to exactly know whether all the pins which are present in 31 00:02:00,930 --> 00:02:04,260 our design are connected to the respective then or not. 32 00:02:04,470 --> 00:02:08,160 You just go in and then perform run synthesis, right? 33 00:02:08,190 --> 00:02:13,670 So this will open up a new planning view where we will be getting the list of use which are present 34 00:02:13,680 --> 00:02:17,820 in our design and whether they are connected to any PGA pin or Rachel. 35 00:02:18,030 --> 00:02:23,900 So as we progress, we will also be understanding one more method that we have to quickly know that 36 00:02:23,940 --> 00:02:26,880 all the pools are connected to their respective right. 37 00:02:26,890 --> 00:02:33,360 So if you utilize any of this pool in your design right, so it will automatically have this yellow 38 00:02:33,360 --> 00:02:35,660 checkmark neighboring to its name, right? 39 00:02:35,670 --> 00:02:41,010 So will be understanding since we are not utilizing any of this will benefit you right now. 40 00:02:41,010 --> 00:02:43,200 So you won't be finding any check mark over here. 41 00:02:43,390 --> 00:02:43,530 Right. 42 00:02:44,400 --> 00:02:51,870 So we will just be waiting for synthesis to complete and analyze I planning where we will even to find 43 00:02:51,870 --> 00:02:56,700 out whether this two pools that are gotten fixed value is connected to their respective right. 44 00:02:56,700 --> 00:03:03,360 So I think this is we will be selecting opens and this is design and will click OK, right now here 45 00:03:03,360 --> 00:03:09,450 you could see by default, we have a device and package you and at the bottom you see and I save. 46 00:03:09,450 --> 00:03:12,870 So I design consist of I fixed, right? 47 00:03:13,110 --> 00:03:19,080 And you could see that these are already being connected to the respect respective have because you 48 00:03:19,080 --> 00:03:20,670 could see to check Mark over here. 49 00:03:20,670 --> 00:03:28,000 And if you just click on this arrow, you could actually observe the events which are there for that, 50 00:03:28,230 --> 00:03:28,460 right? 51 00:03:28,470 --> 00:03:32,010 So this basically suggests that all the benefit. 52 00:03:32,160 --> 00:03:38,040 OK, so here you could see the you, which is also connected to their respective pins. 53 00:03:38,280 --> 00:03:45,440 So whenever you open up an outlining view and as soon as you see checkmark on a fixed tab, we'll get 54 00:03:45,450 --> 00:03:50,370 that basically mean the boot has been connected to the respective FPGA hardware.