What we were so far is spending our CPU clock cycles for some event to happen and then processing the request. Remember our previous labs where we sensed the state of the 4 DIP switches at the interval of 1 second and turn on and off the respective LED's. This approach of serving CPU resources is often referred to as Polling. So polling method requires continuous CPU attention hence we cannot serve other devices waiting for CPU attention assuming we only have Single-Core which processes Instructions.

In a real system, you will be noticing there are numerous sensors and actuators requesting CPU attention at specific times. hence Polling method may be easy to implement but not always suitable for all the applications. Such Scenarios are handled efficiently by Interrupts.

There are two things we need to know

1) At what time the event will happen is a mystery for us ??

2) How to Handle Interrupts ??

We Clasiffy events into two categories viz. Synchronous event and Asynchronous Event.

1) Synchronous Event: This happens when Exception, Unidentified OPCODE, Overflow, Trying to access restricted Memory occurs. Now here the advantage with us is we exactly know when this event will happen and then can write code to handle such an event. This usually happens in Software, so after executing the instruction leading to the cause mentioned above we write handler and the timing problem is solved in this case since we know the next instruction should be Interrupt handler.

2) Asynchronous Event: This event is trigger when the Hardware device requests the CPU's attention hence timings are unknown. The strategy we adopted is the addition of one hardware pin which will tell the CPU about the Event and then we execute a handler.

So Synchronous event happens when something bad happens with software and we can start the execution of the handler just after the Event while the Asynchronous event is raised by Hardware pin any time and then the handler is executed.

The Zynq SOC has a hardened Interrupt controller called GIC(Global Interrupt Controller) which to handle interrupt request from both Hardware and Software. The GIC convey information about interrupt to the CPU, it also prioritizes, mask interrupts.