1 00:00:00,120 --> 00:00:05,370 So the third method that we have, which could be used to communicate the idea for augmenting processing 2 00:00:05,370 --> 00:00:11,850 system to a peripheral is utilizing any essay ideas that are available in and saving state. 3 00:00:11,940 --> 00:00:18,720 So what here will happen is we have a zinc processing system, which will be sending the signal with 4 00:00:18,720 --> 00:00:21,150 any exchange of these to our IP. 5 00:00:21,150 --> 00:00:26,430 No IP will take out the useful data from the interface. 6 00:00:26,550 --> 00:00:28,870 OK, and then it will apply to a peripheral. 7 00:00:28,890 --> 00:00:33,960 So this will be an entire process right now when we considered an IP, so they all will be implemented 8 00:00:33,960 --> 00:00:35,520 in and programmable logic. 9 00:00:35,730 --> 00:00:42,450 So ultimately, this just is that if we have an IP, which could understand the proof that we do not 10 00:00:42,450 --> 00:00:48,660 need to specify a Gulfstream ends, we do need to specify a constrained so will be understanding how 11 00:00:48,660 --> 00:00:49,830 an entire thing work. 12 00:00:49,930 --> 00:00:57,040 Rachel, let me just go ahead and copy the DCL script by first modifying the project as well as the 13 00:00:57,060 --> 00:00:58,400 project territory, right? 14 00:00:58,410 --> 00:01:02,080 So we'll just be copying this and feasting it in. 15 00:01:02,080 --> 00:01:08,260 A. Still coming right now, here we will be again working within a leading switch. 16 00:01:08,280 --> 00:01:14,430 So what we're going to do is we will be reading the state of a slide switch and then we'll be applying 17 00:01:14,730 --> 00:01:17,490 the values that we receive on a straight switch to any lady. 18 00:01:17,520 --> 00:01:18,770 This will be original, right? 19 00:01:18,780 --> 00:01:21,660 So we have a fundamental block design over here. 20 00:01:21,840 --> 00:01:26,370 Now, when we want to communicate the data from processing system to be in. 21 00:01:26,580 --> 00:01:33,990 So we need to add the master essay board to a processing system that is the first thing that we're going 22 00:01:33,990 --> 00:01:34,290 to do. 23 00:01:34,530 --> 00:01:38,820 The second thing is we'll also be requiring clock entry said, OK, so these are the three things that 24 00:01:38,820 --> 00:01:41,870 will be adding to our fundamental high right. 25 00:01:42,180 --> 00:01:45,990 So let me just go ahead and double click on losing processing system to reconfigure it. 26 00:01:46,770 --> 00:01:52,740 Now, when we go to PSP configuration in a general, we see the option to add a reset. 27 00:01:52,740 --> 00:01:57,690 So let it just go ahead to enable clock reset and add one off reset. 28 00:01:57,930 --> 00:01:58,860 This is the first step. 29 00:01:59,280 --> 00:02:03,090 Then we will be going to our next say OK. 30 00:02:03,090 --> 00:02:06,690 And here we have a provision to add Master U.S. this rate. 31 00:02:07,260 --> 00:02:08,750 This is the second thing that we do. 32 00:02:08,760 --> 00:02:11,220 The last thing is the fabric clock rate. 33 00:02:11,230 --> 00:02:19,620 So that will be going to the people IP right to let it just go to a field fabric clock and then select 34 00:02:19,620 --> 00:02:20,240 this clock, right? 35 00:02:20,280 --> 00:02:25,260 So this three modification will be doing to our fundamental Typekit right now. 36 00:02:25,260 --> 00:02:30,510 You could see we have a master essay put there, and this is also to general purpose portrait. 37 00:02:30,520 --> 00:02:32,490 And then we have a clock and we stick. 38 00:02:32,550 --> 00:02:37,470 This will be useful when we want to communicate the data to any off any side. 39 00:02:37,560 --> 00:02:37,890 Right? 40 00:02:38,280 --> 00:02:42,210 Let it just go in and try to add and excite you, Poppy. 41 00:02:42,240 --> 00:02:47,790 Now here we like to piece rate right now will not be working on a multi China first, will be working 42 00:02:47,790 --> 00:02:52,320 on a single channel and then we proceed with discussion on a multi channel rate. 43 00:02:52,650 --> 00:02:56,190 So we will be adding to APIs right to here. 44 00:02:56,220 --> 00:03:02,700 One of an IP will be used to communicate the data to the elderly and other will be used to receive the 45 00:03:02,700 --> 00:03:04,380 data from the success rate. 46 00:03:04,740 --> 00:03:11,610 So before performing a connection automation, what I'm going to do is I'll be specifying which IP will 47 00:03:11,610 --> 00:03:13,200 be working with which. 48 00:03:14,450 --> 00:03:15,950 Device rates or here. 49 00:03:17,450 --> 00:03:22,580 GP, i o will be like, this is you the switch? 50 00:03:22,760 --> 00:03:28,490 OK, so this app will be predominantly working with the switch so we could change the name of an IP, 51 00:03:28,490 --> 00:03:28,700 right? 52 00:03:28,700 --> 00:03:32,480 So we will go, we'll just select an IP and then you get the block property. 53 00:03:32,480 --> 00:03:37,340 So here we'll just be naming this s switch, right? 54 00:03:37,670 --> 00:03:41,990 And the one will be working it down with an alley, right? 55 00:03:43,160 --> 00:03:45,150 Just to talk right now. 56 00:03:45,170 --> 00:03:53,480 Once IP, understand the peripherals that are available, OK, and then it allows us to select the specific 57 00:03:53,480 --> 00:03:56,480 peripheral from an IP that basically means this IP. 58 00:03:56,840 --> 00:03:59,960 I understand the pull down for that specific reason. 59 00:03:59,960 --> 00:04:03,860 We do not need to specify a consumable game that would be clear. 60 00:04:04,550 --> 00:04:08,120 Now we are ready to perform a connection automation first. 61 00:04:08,120 --> 00:04:09,950 We'll just be naming this as a lady, right? 62 00:04:09,950 --> 00:04:13,340 So we have a switch and we have an elite right now. 63 00:04:13,340 --> 00:04:17,700 We could perform collection automation, so we'll just select all the options without waiting much. 64 00:04:17,720 --> 00:04:22,940 Now this will automatically add and smart interconnect OK and reset circuitry. 65 00:04:22,940 --> 00:04:27,680 So you have a reset circuitry and x interconnect, right? 66 00:04:27,680 --> 00:04:29,680 So this tube lopsided are OK. 67 00:04:29,780 --> 00:04:37,520 That would be helpful to communicate the data from the master say to the slave APIs that we have right 68 00:04:37,880 --> 00:04:39,470 now, if you just regenerate Leo. 69 00:04:39,740 --> 00:04:46,190 So here we have a zinc processing system and this clock is being utilized for all the APIs that are 70 00:04:46,190 --> 00:04:46,880 being added right. 71 00:04:46,880 --> 00:04:53,660 So you could see we have across the system reset, which is working on the same clock to say interconnect, 72 00:04:53,660 --> 00:04:55,610 which is also working on the same clock. 73 00:04:55,610 --> 00:04:58,850 And then two APIs are also working on the same clock, right? 74 00:04:58,880 --> 00:05:06,380 The next thing that it requires is a reset to clearly see we have also a reset and then the processor 75 00:05:06,380 --> 00:05:07,250 system reset. 76 00:05:07,250 --> 00:05:11,390 Basically, you need to reset for the rest of the peripheral IP, right? 77 00:05:11,390 --> 00:05:17,420 So the reset signal from losing processing system goes to the processor system reset and then this basically 78 00:05:17,810 --> 00:05:19,670 reset signal for our IP. 79 00:05:19,670 --> 00:05:26,960 OK, so you could clearly see a benefit, a reset which is applied to all the three apps that we have 80 00:05:26,990 --> 00:05:27,960 right now. 81 00:05:27,980 --> 00:05:31,580 This also suggest we have any say in technique. 82 00:05:31,580 --> 00:05:36,800 OK, so we could connect multiple sleeve APIs is doing. 83 00:05:37,430 --> 00:05:44,960 So it doesn't mean that when we see we have a single Master X AGP zero here, so we are allowed to be 84 00:05:44,960 --> 00:05:47,750 connected to a single sleeve in different states. 85 00:05:47,760 --> 00:05:53,950 So utilizing any interconnect, we could connect to multiple three APIs over here again, then enter. 86 00:05:53,960 --> 00:05:55,880 Handshaking has been handled by design. 87 00:05:56,060 --> 00:05:56,360 Right? 88 00:05:56,840 --> 00:06:02,270 So have you considered the leadership for the smart interconnect OK, which we have in its embarrassing 89 00:06:02,270 --> 00:06:02,690 system? 90 00:06:02,990 --> 00:06:07,560 So this allows us to connect up to 16 sleeve interfaces, right? 91 00:06:07,600 --> 00:06:09,380 And 16 mustering devices. 92 00:06:09,380 --> 00:06:16,600 So this also suggests that we are not restricted that Master X AGP zero it will be connected to only 93 00:06:16,730 --> 00:06:18,780 single sleeve 6a b. 94 00:06:18,980 --> 00:06:23,410 By utilizing an exchange to connect, we could connect to multiple sleeve APIs. 95 00:06:23,760 --> 00:06:29,060 Right now, the next step is to count the number of code that we have, so we have one two three four. 96 00:06:29,130 --> 00:06:33,700 Right now, if you go to a boutique, things will become much easier to understand, right? 97 00:06:33,700 --> 00:06:38,210 So this too, we already know, are fixed to their respective site. 98 00:06:38,210 --> 00:06:43,190 And then we do not need to worry because from the beginning, we know that this to by default, get 99 00:06:43,200 --> 00:06:43,910 turkensteen. 100 00:06:44,600 --> 00:06:46,610 We just need to worry about this too, right? 101 00:06:47,060 --> 00:06:51,230 And you could see a little circle is marked a lot. 102 00:06:51,230 --> 00:06:53,720 So this would basically mean we all really connected. 103 00:06:53,720 --> 00:06:58,380 An LLC to their respective pins and switch are also connected to their respective pins, right? 104 00:06:58,400 --> 00:07:01,940 And we do not have any either code present in our design. 105 00:07:02,450 --> 00:07:06,650 So this basically said just all the ports are been connected to their respective pins. 106 00:07:06,980 --> 00:07:11,180 And if you are bit confused about this process, just go ahead and perform the synthesis. 107 00:07:11,180 --> 00:07:17,630 So once you perform a synthesis, you'll clearly understand whether all the ports are connected to their 108 00:07:17,630 --> 00:07:18,380 respective port. 109 00:07:18,380 --> 00:07:24,030 Rate will go to the source that there will be converting a block design to an ideal wrapper. 110 00:07:24,050 --> 00:07:25,670 This is the first step that we follow. 111 00:07:25,940 --> 00:07:33,140 So once we have a wrapper, we will be performing a synthesis just to verify, OK, just to sic cross, 112 00:07:33,140 --> 00:07:36,310 verify whether these are connected to the respective port. 113 00:07:36,320 --> 00:07:42,590 Great, so we won't have is the easiest way to understand whether the ports are connected to the respective 114 00:07:42,590 --> 00:07:43,220 pins or not. 115 00:07:43,220 --> 00:07:50,330 You just need to see whether you get the respective peripheral market with an OK, that is the only 116 00:07:50,330 --> 00:07:50,540 thing. 117 00:07:50,750 --> 00:07:54,910 If you see any luma, that basically means you do not need to specify any constraint, right? 118 00:07:55,370 --> 00:07:59,060 So once all your output is ready, go ahead and perform a synthesis. 119 00:08:00,600 --> 00:08:04,850 So our synthesis is completed now, we'll just go to an open synthesis to see. 120 00:08:05,160 --> 00:08:10,380 And here we'll just quickly or but all the polls have been fixed to their respective sector. 121 00:08:10,580 --> 00:08:14,470 So you could see we have four polls, OK, and all of them are fixed straight. 122 00:08:14,490 --> 00:08:21,180 So this is the second week if you find any confusion analyzing the vote that right now, as this process 123 00:08:21,180 --> 00:08:26,040 is now, since all the polls are connected to their respective sites, we could just proceed generation 124 00:08:26,040 --> 00:08:27,150 of of extreme right.