1 00:00:00,060 --> 00:00:03,640 Once we create a new project, we will be finding with each to this step. 2 00:00:03,720 --> 00:00:10,680 OK, there you get a flu navigator, the suit strap, the properties tab and then at the bottom side 3 00:00:10,680 --> 00:00:14,030 you have a console message log designed, right? 4 00:00:14,070 --> 00:00:20,360 So as you properly sang as and when required to use, any one of this option will be understanding more 5 00:00:20,370 --> 00:00:20,730 on that. 6 00:00:20,820 --> 00:00:25,950 So the target for this specifically do is to understand the flu, navigate the different option that 7 00:00:25,950 --> 00:00:28,050 you see in a flu, navigate, right? 8 00:00:28,470 --> 00:00:33,290 So the first option that you see is our project manager, right? 9 00:00:33,300 --> 00:00:35,970 So inside this, you have two options. 10 00:00:35,970 --> 00:00:41,130 So you have this entire four option that have been included in the project manager. 11 00:00:41,130 --> 00:00:47,610 The first thing that is setting allows to change the language at the right time are pushing 30 by three 12 00:00:47,610 --> 00:00:54,570 to see you have a region where you could perform changes in a project device later on our target language. 13 00:00:55,050 --> 00:01:00,290 But usually once you perform a changing an entire flow, need to be performed right. 14 00:01:01,110 --> 00:01:07,470 So setting allows to change the device in Gingin or the setting related to simulation in operation nine 15 00:01:07,470 --> 00:01:08,130 different pieces. 16 00:01:08,430 --> 00:01:13,980 But the primary use of this will be to change the device or a language if required. 17 00:01:14,010 --> 00:01:14,280 Right. 18 00:01:14,730 --> 00:01:15,450 Then we have an. 19 00:01:16,000 --> 00:01:21,420 So whenever you require to add and as you follow this option, we'll get the services that could be 20 00:01:21,420 --> 00:01:25,520 added as either very low visual art, a system, right? 21 00:01:25,890 --> 00:01:26,910 Then we have a language. 22 00:01:27,270 --> 00:01:33,210 So whenever you are in a specific need to invoke a correct component, for example, addresses in block 23 00:01:33,210 --> 00:01:33,660 many. 24 00:01:34,670 --> 00:01:41,120 So there you need to follow a certain cooling style, so that could be easily this by analyzing the 25 00:01:41,120 --> 00:01:41,900 language template. 26 00:01:41,900 --> 00:01:47,380 So if you just go to a language tabloid and look for the device that you want to implement, such as 27 00:01:47,900 --> 00:01:48,270 Ma'am. 28 00:01:48,560 --> 00:01:54,400 So you get a series of attempting to just follow a template and then you could implement an exact rate. 29 00:01:55,220 --> 00:01:57,020 The next one is an ipecac. 30 00:01:57,230 --> 00:02:02,780 So here you'll be getting a series of IP, which are feed available for the license that you have. 31 00:02:03,830 --> 00:02:07,550 Applied to the right to decide the future option. 32 00:02:07,760 --> 00:02:14,690 Now these are predominantly related to very long and we still call, so we will be skipping this option 33 00:02:14,690 --> 00:02:18,200 in the most part of the course only when we are designing our own IP. 34 00:02:18,380 --> 00:02:20,770 OK, very true, right? 35 00:02:20,990 --> 00:02:21,860 Are very local. 36 00:02:21,960 --> 00:02:25,220 They're only we will be walking around with this option, right? 37 00:02:25,250 --> 00:02:27,050 The second option is an IP integrated. 38 00:02:27,050 --> 00:02:30,090 This allows us to create a block design, right? 39 00:02:30,290 --> 00:02:35,870 And for an embedded system design, this is a standard methodology that is schematic based design very 40 00:02:35,870 --> 00:02:37,550 utilized and IP integrate, right? 41 00:02:37,880 --> 00:02:43,520 So for most of part of the goods, we will be preparing to go with that design. 42 00:02:43,820 --> 00:02:49,910 So you just need to click on create blog design, and this will add the canvas where we can start invoking 43 00:02:49,910 --> 00:02:54,100 an IP use and then create, tie and hydrate, right? 44 00:02:55,430 --> 00:03:01,810 So these are two ways that we have, either you could specify your thoughts in a text based methodology 45 00:03:01,820 --> 00:03:03,570 where you very love me. 46 00:03:03,590 --> 00:03:05,300 Still, our system will good. 47 00:03:05,570 --> 00:03:10,380 And the second one is to add your design into a schematic. 48 00:03:10,530 --> 00:03:14,060 So this idea to design methods that we have is that the first option? 49 00:03:14,570 --> 00:03:21,440 And from this, you could clearly guess that the first step that we do in an BJU based design is to 50 00:03:21,440 --> 00:03:22,550 specify your design. 51 00:03:22,790 --> 00:03:24,110 So there are multiple methods. 52 00:03:24,590 --> 00:03:25,880 Two of them we discussed. 53 00:03:25,880 --> 00:03:33,230 One of them is to add or specify the text based source that is very low still on our system. 54 00:03:34,010 --> 00:03:40,370 The second was to utilize the schematic that is utilizing an IP integrator, but remember an entire 55 00:03:40,370 --> 00:03:40,940 floor? 56 00:03:41,180 --> 00:03:41,540 OK. 57 00:03:42,020 --> 00:03:44,190 We need to have a very local. 58 00:03:44,240 --> 00:03:51,140 So even though we do need the schematic, ultimately we will be creating a wrapper or grew out of it. 59 00:03:51,380 --> 00:03:56,240 And then we are allowed to use this option that you'll see below IP integrated. 60 00:03:56,240 --> 00:03:58,310 The next option that you have is a simulation. 61 00:03:58,730 --> 00:03:59,900 So this is used to. 62 00:04:00,770 --> 00:04:03,320 But far more functional verification of the design. 63 00:04:03,740 --> 00:04:09,350 So usually when we consider any major design, we do not work on a signal level. 64 00:04:09,460 --> 00:04:09,830 OK. 65 00:04:10,580 --> 00:04:16,880 If we wish to work on a signal level, the best choice that we have is entirely will not be performing 66 00:04:16,880 --> 00:04:17,660 simulation. 67 00:04:17,700 --> 00:04:23,870 Look at the signal level and applying a random stimulus because you'll be finding the signals will be 68 00:04:23,870 --> 00:04:25,340 there and approaching. 69 00:04:25,340 --> 00:04:29,570 Each and every combination is next to an impossible right. 70 00:04:29,930 --> 00:04:35,840 So usually either an eyelid, then you want to analyze the signals or a V will be debugging. 71 00:04:35,840 --> 00:04:40,710 Odd applications that are the standard practice actually for the next one is an ideal analysis. 72 00:04:40,710 --> 00:04:44,540 So this give us the idea about the cells that we are utilizing. 73 00:04:44,540 --> 00:04:50,390 For example, when we break down certain they still go to work, all components are invoked light that 74 00:04:50,390 --> 00:04:52,400 could be easily understand by Anakin. 75 00:04:52,400 --> 00:04:58,490 And this is then this give us an idea of either the design that we are expecting is what we are invoking, 76 00:04:58,550 --> 00:04:58,790 right? 77 00:04:59,210 --> 00:05:03,230 Since this is converted into something that our feature in this turn. 78 00:05:03,230 --> 00:05:07,580 So we have certain set of primitives for each FPGA family. 79 00:05:07,760 --> 00:05:09,110 So synthesis transform. 80 00:05:09,150 --> 00:05:15,050 I still call into the primitives, which could be downloaded on an SPG, right? 81 00:05:15,920 --> 00:05:22,100 Then comes an implementation, so the implementation will choose the specific position where we will 82 00:05:22,100 --> 00:05:27,770 be adding a logical UI depending on the preference specified in and const. 83 00:05:28,070 --> 00:05:28,300 Right. 84 00:05:28,310 --> 00:05:30,230 So this is what an implementation do. 85 00:05:30,710 --> 00:05:33,930 Then we have a condition of a bit, right? 86 00:05:33,960 --> 00:05:40,250 So finally, when we download our program, we'll get our logic on to budget and only we will be able 87 00:05:40,250 --> 00:05:41,300 to test on higher rate. 88 00:05:41,300 --> 00:05:47,720 So it requires a bit fight that could be generated by the bitstream option and then open hardware manager 89 00:05:47,720 --> 00:05:54,150 allow us to connect the device either locally or remotely to override. 90 00:05:54,200 --> 00:05:54,420 Right. 91 00:05:54,440 --> 00:05:59,970 So these are the series of options now, since we will not be working on the signal level when we consider 92 00:06:00,000 --> 00:06:00,840 an embedded design. 93 00:06:01,130 --> 00:06:03,020 OK, at least for the most part, of course. 94 00:06:03,200 --> 00:06:09,260 In fact, some of the debugging technique when we tackle there, we will be utilizing annihilate to 95 00:06:09,290 --> 00:06:11,930 capture the signals on the net. 96 00:06:12,590 --> 00:06:15,380 But far less so the case in an embedded system design. 97 00:06:15,380 --> 00:06:19,550 We hardly work on the signal level that is individually triggering a signal. 98 00:06:19,580 --> 00:06:29,780 So simulation analysis, synthesis and implementation are not used when we work with an embedded system 99 00:06:29,780 --> 00:06:30,070 design. 100 00:06:30,080 --> 00:06:35,390 So most of the time what will happen is we'll be creating a block to say we'll be specifying in hybrid 101 00:06:35,390 --> 00:06:45,020 design by adding an IP, then a fire IP do not consist of any unrecognized booed by value. 102 00:06:45,620 --> 00:06:51,850 So what it means will be our understanding in the next video to see if we were able to understand output. 103 00:06:51,870 --> 00:06:57,590 And then in that case, what we will do is it will automatically specify a constraint so we do not need 104 00:06:57,590 --> 00:06:58,690 to do anything right. 105 00:06:59,030 --> 00:07:03,680 In that case, we will directly go to generate stream, so we start to then block the site. 106 00:07:03,980 --> 00:07:10,100 We directly go to Bitstream and then we will be exporting the big filing to an s. 107 00:07:10,370 --> 00:07:11,810 This will be our normal flow. 108 00:07:12,020 --> 00:07:18,710 But if you add an IP whose input and output ports are not recognized by and we do OK usually when we 109 00:07:18,710 --> 00:07:20,210 create our custom APIs. 110 00:07:21,290 --> 00:07:22,310 In that case. 111 00:07:23,650 --> 00:07:29,890 We need to perform a synthesis, OK, and then we need to specify the country, which basically will 112 00:07:29,890 --> 00:07:32,790 tell where you want to connect our input and output. 113 00:07:33,220 --> 00:07:36,960 And then again, we'll be going to the Djindjic Midstream, right? 114 00:07:36,970 --> 00:07:38,120 So this will be our normal. 115 00:07:38,160 --> 00:07:40,200 So we started the block design. 116 00:07:40,210 --> 00:07:48,330 If all the words that we have in our design, if they are defined and understood by we are the way before, 117 00:07:48,340 --> 00:07:52,030 in that case, we will directly be jumping to changed midstream. 118 00:07:52,420 --> 00:07:58,810 The second scenario will be when we have added some of the ports which are not going to stand by and 119 00:07:58,810 --> 00:07:59,110 we are. 120 00:07:59,320 --> 00:08:01,530 This will happen when we create custom APIs. 121 00:08:01,540 --> 00:08:08,740 So in that case, we will be starting with a create block design, performing a synthesis, specifying 122 00:08:08,740 --> 00:08:11,310 the poofs and then generating a mixture. 123 00:08:11,620 --> 00:08:18,490 So this will be I flues know when we started that embedded system design using the Viper.