1
00:00:00,060 --> 00:00:07,500
So when we are creating a new project design, the seeds of project that we now will discuss fundamental

2
00:00:07,500 --> 00:00:08,220
of each of them.

3
00:00:08,230 --> 00:00:10,470
So you have an idea of why we have choose it.

4
00:00:10,680 --> 00:00:12,900
And I do, but I feel project great.

5
00:00:12,900 --> 00:00:15,150
So fostering that we have is an example project.

6
00:00:15,150 --> 00:00:23,640
So here we have a set of an example project to deal with, and we value by default rate for each specific

7
00:00:23,880 --> 00:00:24,960
FPGA family.

8
00:00:24,960 --> 00:00:31,320
So if you want to build your project on top of it, you basically proceed with an example project.

9
00:00:31,570 --> 00:00:39,630
So you get a set of school block design and a school hook, which could be utilized and modified according

10
00:00:39,630 --> 00:00:40,560
to your requirements.

11
00:00:40,740 --> 00:00:45,570
So this is the first option that we have, which is example project, right?

12
00:00:45,990 --> 00:00:47,730
Then we have an important project.

13
00:00:47,740 --> 00:00:56,280
So if you have developed your design into either a simplified, existing or nice, in that case, this

14
00:00:56,280 --> 00:00:58,300
option allow us to expand that into.

15
00:00:58,870 --> 00:00:59,130
Right.

16
00:00:59,130 --> 00:01:01,410
So this is the second option that we have.

17
00:01:01,590 --> 00:01:04,400
The third option is a new planning project to here.

18
00:01:04,880 --> 00:01:09,240
Let us assume you have not yet developed your idea, right?

19
00:01:09,240 --> 00:01:16,770
So your land, they lock all their design that you have in an IP is not yet been developed, but let's

20
00:01:16,770 --> 00:01:23,180
assume you want to fix it and you think that you have one an SPG two specific benefit.

21
00:01:23,190 --> 00:01:30,090
And so that the team, which is working on developing off and BCB OK, our developing board could work

22
00:01:30,090 --> 00:01:33,970
in parallel with the team that is developing an idea.

23
00:01:33,990 --> 00:01:40,200
So in that case, what we do is we fixed the Europeans that we have on an FPGA to this specific benefit

24
00:01:40,950 --> 00:01:47,340
so that the team, which is developing a development mode, could work around in parallel with a team

25
00:01:47,340 --> 00:01:48,630
that is developing an ideal.

26
00:01:48,630 --> 00:01:50,360
And we could see what time, right?

27
00:01:50,380 --> 00:01:56,040
So this is where are you planning project could be very useful, so you could just specify the Europeans

28
00:01:56,040 --> 00:01:58,650
that you have on an FPGA for a specific.

29
00:01:59,680 --> 00:02:05,490
Benefited and then later on, you could start building an ideal world for.

30
00:02:05,620 --> 00:02:07,500
Right, so this is the third option that we have.

31
00:02:07,510 --> 00:02:09,850
The food option is the food synthesis project.

32
00:02:09,850 --> 00:02:17,590
So you ladies, as you have developed a project in a third party software which basically give you and

33
00:02:17,590 --> 00:02:18,910
NGC five, right?

34
00:02:18,910 --> 00:02:25,660
So if you want to test that specific design down to a value, in that case, you could utilize the pool

35
00:02:25,660 --> 00:02:26,820
synthesis project, right?

36
00:02:26,830 --> 00:02:34,000
So this allows us to utilize the BRI synthesis file, which are to have looked in a third party software

37
00:02:34,000 --> 00:02:36,160
and to test them on to an FPGA.

38
00:02:36,190 --> 00:02:36,380
Right.

39
00:02:36,400 --> 00:02:37,900
So this is the food option that we have.

40
00:02:38,350 --> 00:02:40,240
The final option is an ideal project.

41
00:02:40,240 --> 00:02:47,470
So here we could developed and articles we could develop the block designs utilizing an APIs and then

42
00:02:47,470 --> 00:02:49,210
perform an entire design, right?

43
00:02:49,210 --> 00:02:56,020
So out of this file to really see we are not utilizing an example project of and we do, we are also

44
00:02:56,020 --> 00:02:59,970
not importing that project from an IEC or any society.

45
00:03:00,250 --> 00:03:07,660
We are also not performing and planning prior to developing an idea, or we are not also invoking and

46
00:03:07,660 --> 00:03:08,800
intensifying hence.

47
00:03:09,960 --> 00:03:16,710
We could directly go with an ideal project, and this allows us to either ride the tech space designed

48
00:03:16,710 --> 00:03:24,570
such as a venue, lock our system, or you could also have a block design such as an embedded system

49
00:03:24,570 --> 00:03:31,250
design, and then you could convert them to an ideal finally, which could be downloaded on my speech.

50
00:03:31,410 --> 00:03:31,560
Right.

51
00:03:31,570 --> 00:03:34,880
So this is why we have choose in our ideal project.

52
00:03:34,890 --> 00:03:42,210
Just give us an access to creating a block design, which serve as in hardware for our embedded system.