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So in this first video, what will be understanding its will be completing an entire floor walk right

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from creating a project till downloading a project onto an FPGA.

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OK, so this will give us an idea of fundamental idea of an entire floor will not be discussing any

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step in a greater detail right now.

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Our agenda will just be to go through a process because as we progress will be finding, we are building

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up our experience and agree to deteriorate.

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In fact, in next June, you will be understanding some of the options why we are doing that.

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But for this specific, we will be focusing majorly on the process, right?

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So we already started to provide this could be done by just double clicking on the like, and that has

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been added by default.

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OK, when you complete an installation.

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So here I am utilizing the vital two thousand eighteen point three, right?

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We start with the Create project.

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This is the first step that we do know whenever we start creating a new project.

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Here you do see two more option open projects, so this will be utilized when you already have an existing

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project being created.

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All of you are doing, you want to open a door.

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And if you want to look for the example project provided by default with an IED, you could just glue

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for the open example project.

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Great.

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We click next.

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Then we get an option to select a directorate, right?

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So once you select the directory, there are multiple folders will be created required for performing

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a different process.

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All finished speaking.

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Right.

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So here I have chosen the project name, which is by default, Project White and then the location where

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I'll be storing a project right click next.

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Now here you see a fire option by default will be choosing an ideal project.

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Later on, we'll be discussing what each of an option will do for it.

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But here we will proceed with an actual project, and in most of the time, we will be proceeding with

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the Nortel project right next.

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So here, the target language that we'll be using is very low simulator languages mixed, and we won't

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be creating any file because we will be predominantly working on and we will do IP integrator.

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So dare we design our block?

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And then we will be generating in code out of the crate so we do not need to specify any SD.

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So once we complete our IP related work, OK, and we start building our own IP to interface with anything

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there, we could add a create file, but at least for a few sections, will not be doing it right click

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next.

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Considine will be understanding later on what situations we need to add a constraint, but when we consider

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it an IP which recognizes our there, we do not need to add a constraint, right?

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So here we will be.

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Skip this process of adding if constraint, you need to select the correct that is the mandatory step,

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because word file plays a very important role in recognizing your preference when you add an IP, right?

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So the word that I have with me is saying take two seven one zero, so I'll just be selecting that word

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and then proceeding ahead, right?

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So this is the word that I have with me.

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You could select any other see if you have, as I would say, seven to zero or Zabel.

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You could select your respective work, click next and then hit finish.

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No, this will add the necessary folders, which are required at a different.

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Steps when we perform an FPGA right now, you are inside and we board wildly, so you see a small step

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where you'd be finding all the sources are OK and then flew.

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So this plays a very crucial role.

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We'll be discussing each and every step as we progress right now.

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We start with creating a blog designed, so the second option that you have is create a blog detailing

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the first option.

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Allow us to hide of a lot of your total order system relaxers.

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But since we are not writing it right now, we'll be proceeding to a next option.

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OK, which is an IP integrator, so we'll take on create blog design.

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We'll stick to our deployed name, which is design one, and then we'll proceed.

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So here we have a block design, you click on this plus button or this splatter pattern to add an IP

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rate to the processing system for us who will be using.

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So it will just be searching for letting processing system and double clicking on it will add the zinc

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IP onto a canvas, right?

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Once you add the zinc IP, the next step is to perform a block or permission.

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Know what block automation do will be.

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Understanding later on will just be clicking on block automation.

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We'll be keeping our default option, which are checked by default.

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So you have a processing system which just check a pliable preset, which is also checked, and then

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we will be clicking on for this first video.

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We will be working around Gaudin.

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You are right.

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So along with the you what you could see, there are various peripheral which are enabled by default.

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So we require that each year there will not be disabling it.

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But fixed style.

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We only require to work on a new lock, right?

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So if you just double click to reconfigure an IP?

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OK, so here the easiest way is to just look for a block design.

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So all the peripherals which are having a checkmark, I've been enabled by default when we are pliable

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preset, right?

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So you what is Enable GPI is Enable SD card is Enable USB is Enable.

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Ethernet is enabled by default and space also enabled by default, right?

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So you could just go ahead and double click on any of the block which you want to disable.

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So I'll just be double clicking on GPI.

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OK, and this will take you directly to the specific tab, which allows us to disable our different

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option, right?

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So we do not want tonight.

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We do not want the USB SD, we want you out because we will be working around with it, and then we'll

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also be disabling the rest of the basic right.

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So this is the first step where we just enable and you are right, this is the first step that will

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be doing.

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The next thing is, if you just go to a peripheral view, OK, you have a card s.p.a.

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So we do not want to use it will again be disabling it.

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Now, when we consider B is truepill configuration, so we have our IP that will be interface with that

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X8 interface, right?

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So all APL, we have an IP and then all piece, we are required to have any kind of issue in a PSP configuration.

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You will be finding all the default option that allows us to interface the APL APIs OK to the processing

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system and by default, if you just analyser block data.

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So we do have one of the eixa interface, which is enabled by default that is makes AGP zero, but we

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are not targeting any IP over here, so we'll just be disabling it.

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If you just go to IXI non-secure enablement, OK, and then here we have a cheap master A.S. So we'll

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just be I'm checking it, then we haven't been able, Slovic say, even in high performance leveque

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weeks.

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So this will be by default check rate peripherals.

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We already selected a new OK.

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OK.

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The next thing is a clock configuration, because you do see that we have one off the clock port, which

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could be utilizing and plb is been added.

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But since we are not adding any IP, we'll just go to a clock configuration and then you have a pale

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fabric clock, so you just uncheck it, right?

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So those are some of the options that we need to disable.

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And then we click, OK.

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OK.

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So once you do this, you'll be fine.

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If we are left with a limited number of peripherals and as well as few ports are been by default remote

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which have been added, then we both on mobile automation, right?

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The next thing is to clean up a diagram.

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So to do that, we have a region regenerate out over here, right?

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Will just be clicking on it so it will clean up our diagram.

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And then once we complete our block design, the next step is to verify whether all the mandatory connections

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are made to their respective work, right?

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So to do that, to perform a verification, we just need to click on validate design.

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So once validation is successful, once you get this message, the validation successful and there are

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no more headers or a critical warning in the design, you could proceed with a generation of and still

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code, right?

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Remember an entire flow that you are seeing on and through navigate to work on and.

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So we could not directly use of log design.

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So first, we need to convert the block design to NHL code and then only we could proceed with the steps.

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We go to a small step.

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So we go to a small step.

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Right click on the blog to say this is our block design and then create an HDL wrapper.

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So this will change and still cool for us, which will be utilizing to complete the rest of the process.

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One good part about we.

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Is when you do not had a user specific IP, so we automatically create a constraint for us, for example,

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here.

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We created a block automation and then we able to see this very right, so we haven't added anything

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which.

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Seeing do not understand yet, or we do not understand yet.

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OK, so we do not need to add a constraint because once a block automation create opportunity for us

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by default, it also recognised and rate of to where we need to connect dispute.

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Right.

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So whenever?

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Vital recognize the ports that has been created by default, we do not need to specify a constant rate,

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and that is an advantage, as we will be discussing more on this as we build this.

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But here we have not added any user specific IP or user defined IP yet, which is not recognized by

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the light.

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So we do not need to add a constraint.

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Remember this fact into me?

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OK.

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And then once you are still called Israeli now we are ready to perform all the process, right?

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And since we are not working on adding a constraint because constraints are already added by default,

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we could just proceed with the addition of a bitstream.

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So this will automatically perform synthesis implementation, then generation of a bitstream which could

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be utilized to.

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Downloading hardware image on an FPGA.