1
00:00:00,120 --> 00:00:05,950
I've seen this is a successfully completed now we proceed to open a synthesis site right now.

2
00:00:05,970 --> 00:00:12,180
This will allow us to analyze all the pools that we have in our design, where we could add the specific

3
00:00:12,720 --> 00:00:18,060
pool, which are unconstrained to the specific pain of any Fiji, right?

4
00:00:18,210 --> 00:00:23,310
So will allow the synthesis design to open, and this will automatically reflect all the pools which

5
00:00:23,310 --> 00:00:24,480
are present in our design.

6
00:00:24,750 --> 00:00:27,380
And we already know that from a master file.

7
00:00:27,390 --> 00:00:30,120
So we want to collect V.W and to analyze zero.

8
00:00:30,450 --> 00:00:38,010
So the unique number that we get for that when it's you 60 right now here, you could see all the pools

9
00:00:38,010 --> 00:00:39,780
which are present in our design, right?

10
00:00:39,780 --> 00:00:46,170
So 6:00, which is already fixed reset, which is also already fixed and USB light is also fixed.

11
00:00:46,170 --> 00:00:53,250
So one of the scalable which is not connected to anything is the P.W right, and it is having an --

12
00:00:53,250 --> 00:00:53,820
of an output.

13
00:00:53,820 --> 00:01:01,670
So we'll just go ahead to a package and we will debut 60 OK and then we will just be changing the oil

14
00:01:01,680 --> 00:01:02,940
we see more celebrity to be.

15
00:01:03,170 --> 00:01:05,790
We see more sturdy base of with this modification.

16
00:01:06,090 --> 00:01:07,710
We just need to press control controls.

17
00:01:09,110 --> 00:01:11,750
So this will ask us whether we want to see and.

18
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Constraint will just hit OK and will name this stop.

19
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So if you have an existing constraint already and you get this option, also enable that to select an

20
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existing file.

21
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And here you will be showing the extensive file that is present so we could just select that and click

22
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OK, and that will update our existing constraints.

23
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So here we do not have any constraint by representing our design, so we'll just be creating a new constraint

24
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plate.

25
00:01:38,220 --> 00:01:39,540
And we need a desktop.

26
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Click OK with this.

27
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Now, if you go to a source that you could see in a constrained app, you have a top down text you see

28
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and inside that the pin, which is BW am, is been attached to this specific pin on an FPGA, right?

29
00:01:54,960 --> 00:01:58,710
So with this now you could see all the pins been fixed rate.

30
00:01:58,710 --> 00:02:00,000
So this clock is fixed.

31
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Reset is fixed.

32
00:02:01,440 --> 00:02:05,070
The USB part is also fixed and readable, then is also fixed.

33
00:02:05,070 --> 00:02:09,060
So this basically mean all the pools are being connected to the specific pin.

34
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And now we are ready to proceed for generation of which.
