1
00:00:00,060 --> 00:00:05,370
So I've seen this is a successfully completed will just go ahead and select open synthesis design and

2
00:00:05,370 --> 00:00:06,210
click OK, right?

3
00:00:06,210 --> 00:00:09,750
So this will automatically open up the device and package you.

4
00:00:09,750 --> 00:00:15,750
And along with that, we are also able to analyze those key labels which are present in our design.

5
00:00:17,160 --> 00:00:24,670
OK, so here we have our iReport, and you could see our design consist of one, two, three and four

6
00:00:24,700 --> 00:00:25,260
course rate.

7
00:00:25,470 --> 00:00:30,610
And here, if you observe all of them are fixed to their respective pin rate.

8
00:00:30,960 --> 00:00:39,810
So whenever you perform a synthesis, OK, whenever you perform a synthesis and observe this on the

9
00:00:39,810 --> 00:00:45,960
iReport, you could see that all the ports have been correctly mapped to their respective right.

10
00:00:46,470 --> 00:00:51,780
With this, we are ready to perform generation of a good stream, so we'll proceed and.