1
00:00:00,060 --> 00:00:05,810
So synthesis is successfully completed, we go ahead and we click on open synthesis to say, OK.

2
00:00:06,060 --> 00:00:09,450
And this will automatically open the door for new planning.

3
00:00:09,450 --> 00:00:11,840
We're right where we will be finding this killer.

4
00:00:12,300 --> 00:00:20,010
OK, where all the alleles will be added and there we need to perform additional and if it right, so

5
00:00:20,010 --> 00:00:24,120
we'll go ahead and allow a synthesis design to open.

6
00:00:25,850 --> 00:00:31,610
Now, if you see we have a Swiss clock, which is already been fixed, reset has already been fixed.

7
00:00:31,900 --> 00:00:33,680
USB, you are also fixed rate.

8
00:00:34,000 --> 00:00:38,720
A lady is not fixed, so we'll just select the level they use a level two.

9
00:00:38,720 --> 00:00:40,840
Will we see most three way?

10
00:00:40,880 --> 00:00:43,160
That is the first modification that we do.

11
00:00:43,160 --> 00:00:49,820
The next one is to add the pin to each elevate support this week to the help of an exclusive way and

12
00:00:49,820 --> 00:00:53,540
connect the package been to each entity, right?

13
00:00:54,350 --> 00:00:56,180
So we go ahead and for a.

14
00:00:57,050 --> 00:00:57,360
OK.

15
00:00:57,410 --> 00:00:58,780
We have been number 11.

16
00:00:58,800 --> 00:01:00,860
That is what we're going to specify over here.

17
00:01:01,590 --> 00:01:08,640
So likewise, OK, what we're going to do is we'll add the pin for all the bits of the LCD, right?

18
00:01:08,660 --> 00:01:13,660
So I've connected all the LCD panels to the respective hardware in the date.

19
00:01:13,670 --> 00:01:17,300
With this, we'll just be saving our constituents or breast controllers.

20
00:01:17,630 --> 00:01:17,960
OK.

21
00:01:18,140 --> 00:01:21,950
So since we do not have an existing constrained flight, we were clueless.

22
00:01:21,950 --> 00:01:26,390
Whether you want to create a new X DC, well, so we just selected it's justified.

23
00:01:26,700 --> 00:01:28,360
You will just need this test, right?

24
00:01:28,690 --> 00:01:31,430
So now if you go to a small step, OK?

25
00:01:32,000 --> 00:01:39,530
And also the screen folder, OK, here we have our topics justified and you will clearly observe all

26
00:01:39,530 --> 00:01:46,100
the leadership in the map to they you higher rates of additional all the pins are fixed so we could

27
00:01:46,100 --> 00:01:49,310
go ahead and indeed bitstream, right?

28
00:01:49,310 --> 00:01:52,580
So this will be your procedure when you add your own boot.

29
00:01:52,580 --> 00:02:00,350
So can we do not recognize the specific hardware where you want to connect that right?

30
00:02:00,350 --> 00:02:02,650
In that case, you need to perform a synthesis.

31
00:02:02,930 --> 00:02:05,630
You need to open an eye opening group again.

32
00:02:05,660 --> 00:02:11,360
There you need to specify the FPGA pin where you want to connect the respective.