So synthesis is successfully completed, we go ahead and we click on open synthesis to say, OK.
And this will automatically open the door for new planning.
We're right where we will be finding this killer.
OK, where all the alleles will be added and there we need to perform additional and if it right, so
we'll go ahead and allow a synthesis design to open.
Now, if you see we have a Swiss clock, which is already been fixed, reset has already been fixed.
USB, you are also fixed rate.
A lady is not fixed, so we'll just select the level they use a level two.
Will we see most three way?
That is the first modification that we do.
The next one is to add the pin to each elevate support this week to the help of an exclusive way and
connect the package been to each entity, right?
So we go ahead and for a.
OK.
We have been number 11.
That is what we're going to specify over here.
So likewise, OK, what we're going to do is we'll add the pin for all the bits of the LCD, right?
So I've connected all the LCD panels to the respective hardware in the date.
With this, we'll just be saving our constituents or breast controllers.
OK.
So since we do not have an existing constrained flight, we were clueless.
Whether you want to create a new X DC, well, so we just selected it's justified.
You will just need this test, right?
So now if you go to a small step, OK?
And also the screen folder, OK, here we have our topics justified and you will clearly observe all
the leadership in the map to they you higher rates of additional all the pins are fixed so we could
go ahead and indeed bitstream, right?
So this will be your procedure when you add your own boot.
So can we do not recognize the specific hardware where you want to connect that right?
In that case, you need to perform a synthesis.
You need to open an eye opening group again.
There you need to specify the FPGA pin where you want to connect the respective.