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Hello fellas.

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Welcome back.

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In this lesson we're going to talk about the concept of pipelines.

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Basically a pipeline is the mechanism a risk process or users to execute instructions using a pipeline

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massively speeds up execution by fetching the next instruction while other instructions are being decoded

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and executed.

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One way to view a pipeline is to think of it as an automobile assembly line with each stage carrying

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out a particular task to manufacture the vehicle defect lows and instruction for memory the decode identifies

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the instruction to be executed and the execute processes the instruction and write the results back

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to register.

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This is a very simple pipeline.

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It is a three stage pipeline similar to the one used in Codex M and seven process source.

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Here is a sequence of three instructions being fetched decoded and executed by the process or it construction

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takes a single cycle to complete.

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After the pipeline is filled as we can see the three instructions are placed in the pipeline sequentially

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in the first cycle.

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The process or fetches the art instruction from memory in the second cycle.

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The process of fetches the swap instruction and decodes the art instruction in the third cycle.

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Both this up and add instruction are moved along the pipeline to add instruction is executed to sop

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instruction is decoded and they compare or see MP instruction is fetched.

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This procedure is called Fill in the pipeline.

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The pipeline in effect allows the corps to execute on instruction every cycle.

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As I mentioned this is a simple three stage pipeline architecture.

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Some implementations of the pipeline architecture are used in some cores like the cortex a family used

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in devices like the iPhone and other smartphones have as many as 15 stages as the pipeline length increases

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the amount of work done at each stage is reduced which allows the process or to attain higher operating

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frequencies.

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This in turn increases the young the performance and the system latency also increases because it takes

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more cycles to fill the pipeline before the call can execute on instruction.

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The increased pipeline length also means there can be data dependency between certain stages and we

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can write code to reduce this dependence using instruction scheduling which we shall explore in future

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sections.

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The pipeline has not processed on instruction until its past is complete the through the execute stage

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in the execute stage the program counter register always points to the address of the instruction being

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executed plus 8 byte and this corresponds to the fetch stage of the pipeline.

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In other words the piece always points to the address of the instruction being executed plus two instructions

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ahead.

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There are three other characteristics of the pipeline worth mentioning.

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First the execution of the branch instruction or directly modifying the course is the Army Corps flush

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its pipeline.

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Also some arm architectures like the arm 10 uses the branch predictor which reduces the effect of pipeline

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flush by predicting possible branches and loading the new branch address before the execution of the

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instruction.

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Finally the instruction in the execute stage will complete even though an interrupt has been raised.

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Other instruction is in the pipeline will be abundant and the process will start fill in the pipeline

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from the appropriate entry and defect a table.

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So this all there is to its fellows and I shall see you in the next lesson.