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Hello.

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Welcome back.

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The cortex and family differs from earlier designs like the arm 70 then my buddy program this model

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is remarkably similar.

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The process of course are very small generally for the cortex and family members and it's implement

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only some of them.

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Some of the cortex end process or implement only a subset of the instruction set.

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What if some instruction sets the cortex has fewer physical registers compared to the 70 TMI.

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However the 16 registers in the seven TDM I use a mode are the same as the first 16 registers of the

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cortex and register bank the cortex M has 17 general purpose registers 1 status register and 3 interrupt

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mask registers are 0 through are twelve are the general purpose registers these registers as we discussed

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earlier can hold any value you want they can hold in a set to bids value in fact they can hold time

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of values variables if undesired in a field tell you can keep the fields of coefficients in them acts

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of terror are 13 are 13 over here is known as the young the stock point to register and it is a special

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function register the stock point register is actually banked as we shall see there is the main stack

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pointer and the arm there is the main stack pointer and the process that pointer It's a bank to register

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our 13 over here there is the MSP and the PSP the MSP use the main stack pointer and the PSP is the

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process stack pointer our 14 is the link register and it is also a special function register it hosts

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the return address off a subroutine or an exception AR 15 as the program counter register it is the

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third special function register and it points to the instruction being fetched in the pipeline the express

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our register is known as the program status register and you will understand why we have X here in a

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minute the Express are the prime mosque the fourth mosque the base PRI and the control registers are

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special registers these registers are different from the special function registers and because they

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are special registers we have to access them using special instructions such as the MRF which is used

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to read from a special register and the MSR which is used to write into a special register which we

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shall experiment with the X PSR performs the same function as the CPS are indeed serving today my process

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all but with different fields the entire register can be accessed once or you can examine it in three

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different ways the Express are is actually three registers D they are the API are the PSR and the IP

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yes are the AP s are simply stands for the application program status register the PSR means the execution

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program status register and the IP SA means the interrupt program status register the AP SAR the EPA

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are and the IPA are are just specialized for use of the same register the APIs are contains the status

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flags and C and the greater than or equal flags and another flag known as the sticky flag the Q flag

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used in saturation arithmetic which we shall be working with sticky means that the bids can only be

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cleared by explicitly write in 0 2 this bit the IPA SA contains only an exception number that can be

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used in handling forms and other types of exceptions the EPA SA contains the I T also known as the if

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den bit which overlaps with the interrupt continuation bids it also has the bits known as the T bit

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and this t that stands for the thumb bit in future sections we shall use the D I T bit the IFT in in

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our loops when we start coding.

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So in summary the end bit is called the negative bit and it sets high when every sort is negative the

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C is known as D zero bits and it sets high when a result is equal to zero the C is known as the carry

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bit V is the overflow bit and so on.

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We shall explain these flags further when we applying them in our code.

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So this is all there is to it and I'll see you in the next lesson.