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Hello.

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Welcome back.

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In this lesson we should talk about registers.

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Registers are just the most fundamental storage area on the chip.

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You can put almost anything you want on a register.

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Data Values like time of values COUNTER LIST tables and so on and so forth.

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Process or solve a number of registers inside a process of call.

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And most of these registers are grouped in a unit known as the register bank.

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The 70 PMI process has a total of 37 registers and 30 of these registers general purpose registers six

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of them are status registers and one is the program counsel register the arms of registers are arranged

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in partially over Lapin banks meaning you as the program I see a different register bank for each process

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or mode.

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Sometimes this creates a bit of confusion but it shouldn't really simply put out at any time.

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Fifteen general purpose registers 1 or 2 status registers an AR 15 which is known as the program counter

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register visible to you.

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Ask the programmer you always programmed these registers using the same name but dependent on which

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mode you are in.

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You are simply looking at different sets of registers as you can see here.

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They use a mode over here you have our issue through our 14 program counter register and a current program

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status register C P S R for sure.

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This is what the end of the table looks like.

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Actually so as you can see there CPS are actually this a smaller version of the tables.

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Let's use this one.

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If the process are way to suddenly change to the abort mode for whatever reason it would swap or bank

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out registers are 13 and are 14 with different r 13 and our 14 registers.

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Notice that the largest register swaps occurs when the processor changes to the fast interrupt mode.

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This is partly because the processor is trying to do everything very quickly saved a state of the machine

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and restore a new state during an interrupt.

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It is normally necessary to drop everything the process is doing and begin to work on one task and this

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involves even the state of the machine in transition to handling the interrupt very quickly rather than

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moving the data from all the registers on the processor to extend or memory.

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The machine simply swapped certain registers with new ones to allow the programmer access to fresh registers.

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I know this may sound a bit unusual but way to get to the section on exception handling the banked registers.

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Those cheated Gray they are available when the processor is in a particular mode.

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For example sports mode has banked registers are 13.

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I bought an AR 14 I bought and SPDR I bought.

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As you can see every process or more would accept the use a mode can change mode by writing directly

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to the the mode bit of the CPRS register which we shall examine later or process and modes accept the

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system mode have a set of Associated Bank registers that are a subset of the main 16 registers at bank

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register maps one to one onto the user mode register.

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So if you change the process a mode at bank register from the new mode will replace the existing register.

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While most of the registers can be used for any purpose there are a few registers that are normally

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used for special purposes.

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R 13 is known as the stock pointer register and it hosted the address of the stack in memory and a unique

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stack pointer exist for each mode.

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We shall examine this incoming lessons our 14 is known as the link register and it is used to hold these

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subroutine or exception return address AR 15 hosted the program counter and we shall we shall see the

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at the end of this section.

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Both the 70 PMI and the Caltex pipeline architectures meaning that while one instruction is being fetched

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another is being decoded and yet another is being executed.

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The address of the instruction that is being fetched is contained in this AR 15 known as the program

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counter register.

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You ask the programmer once normally access this register on less than certain specific cases where

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let's say you need to jump to a particular memory location or when you want to recover to a different

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destination after an interrupt.

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We shall experiment with all of these later.

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The CPS R is also known as the the current program status register and can be seen as a state of the

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system allowing the program to recover from exceptions or branch on the result or an operation it contains

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condition flags interrupt flags the current mode and the current state.

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Each privileged state has a saved program status register as we can see in the diagram here.

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Each privilege mode has its own SPSS.

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The supervisor has SPSS R as FEC a poor test S P S R a port on defined whose spirits are undefined etc.

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The SPSS R is used to save the value of the CPS R when an exceptional case since use a mode and system

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mode are not entered on any exception.

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They do not have an espresso and a register to preserve CPS are is not required for these modes.

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Actually in the use of motor system would if you attempt to read DSP SPSS you will get on an unpredictable

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value back meaning the data cannot be used.

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And if you attempt to write to the SPSS register in one of these most that data will be ignored.

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These four bits at the top here are collectively known as the condition code flags and the 8 bits at

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the bottom also a condition could fly can be altered by the arithmetic and logical instructions such

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as subtraction addition logical shift etc..

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We shall examine the meaning and relevance of these in our code.

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The F and a bit here.

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The interrupt to disable bits which disable the fast interrupt in the normal interrupt.

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If the asset the TBD is known as the status bit and it is used to indicate the state of the system so

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you ask the programmer will only read this bit not right to it as we shall see later.

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There is a different requirement associated with this bit when it comes to the cortex and architecture.

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If the bit is set to one it means the core is executed and in thump mode.

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The list significant bits are used to set the.

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The mode of the processor.

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When bit 4 through 0 are set at 1 serious serious serious 0.

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Then the process is set to operate and use a mode in the same way.

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When these bits set at 1 0 0 0 1.

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Then the process operate and fast interrupt mode and in the same way when all four data set when 0 5

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bits remember its bid for 3 0.

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So when all 5 bits are set at 1 1 1 1 1 then the system is operating in the system mode.

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So this all there is to it and I'll see you in the next lesson.