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Hello.

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Welcome back.

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So in this lesson we should talk about the generic architecture behind interface and power flows to

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the process or as you may know embedded systems that interact with the the outside world needs some

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form of peripheral device.

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In a sense the set of peripherals attached to the embedded device determines the uniqueness of the arm

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of that device.

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All upper floors are memory mapped and this means the programming interface is a set of memory address

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registers.

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And as we shall see when we begin coding the address of these registers is an offset from a specific

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pair for base address.

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Our simplified embedded device over here still shows two items we've not talked about.

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We've explained the process all we have explained the eight HP and the APB buses.

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We've talked about memory.

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We've said the green rectangles are just examples of some peripherals that can be connected to the embedded

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device.

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We are left with the memory controller and the interrupt controller the memory controller simply connects

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that different types of memory we talked about to the processor.

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For example when the power is turned on the memory controller may be configured in hardware to allow

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certain memory devices to be active.

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These memory devices allow the initialization code to be executed.

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Some memory devices must be set up in software though something like the under D ROM we first have to

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set up the memory timings and the refresh rate using software before it can be accessed.

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Now about the interrupt controller it is basically it's basically determines which peripheral can access

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the process or at specific times.

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There are two types of interrupt controllers available in the standard interrupt controller and DRM

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defected interrupt controller.

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I shall leave the discussions on interrupt controllers for the V for the future lessons when we're talking

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about interrupt only.

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So this is all there is to it and I shall see you in the next lesson.