1 00:00:00,630 --> 00:00:01,120 Hello. 2 00:00:01,170 --> 00:00:02,160 Welcome back. 3 00:00:02,160 --> 00:00:08,850 So in this section we're going to learn about this serial peripheral interface which is known as SBA 4 00:00:08,850 --> 00:00:10,120 for short. 5 00:00:10,140 --> 00:00:17,650 Also another name for this serial powerful interface is the synchronous serial interface. 6 00:00:17,760 --> 00:00:24,980 SS I for short so if you see SBI denoted us SS by it's the same thing. 7 00:00:25,530 --> 00:00:32,870 SBA allows microcontrollers to communicate asynchronously with peripheral devices and other microcontrollers. 8 00:00:33,390 --> 00:00:38,640 We can operate the SBA system as either master or slave. 9 00:00:38,640 --> 00:00:45,390 Before we talk more about the SBA let's compare it to the new art and see the key differences. 10 00:00:45,390 --> 00:00:51,630 The new art allows asynchronous communication and that is why it is called a universal asynchronous 11 00:00:51,630 --> 00:00:53,490 receiver transmitter. 12 00:00:53,490 --> 00:00:57,060 The SBA allows synchronous communication. 13 00:00:57,060 --> 00:01:02,430 This means that to a device is communicating whether you are to operate the same frequency which we 14 00:01:02,430 --> 00:01:10,620 call the default rate but have split but have separate clocks with you at the clock signal is not included 15 00:01:10,680 --> 00:01:14,300 in the interface cable between devices to you. 16 00:01:14,300 --> 00:01:21,390 Art's devices can communicate with each other as long as the clock frequencies or bulk rate is within 17 00:01:21,390 --> 00:01:24,800 plus or minus 5 percent of each other. 18 00:01:24,900 --> 00:01:30,940 On the other hand two devices communicating with SBA operate from the same clock source. 19 00:01:31,350 --> 00:01:38,040 Typically the master device creates the clock and a slave device uses the clock to latch data in and 20 00:01:38,130 --> 00:01:39,980 send data out. 21 00:01:39,990 --> 00:01:44,760 The SBA typically consists of four wives or four pins. 22 00:01:44,760 --> 00:01:58,650 These are the is the eye the SD or the S C O K and the C in many chips the S D I S D or s C.L. kit and 23 00:01:58,910 --> 00:02:07,660 seeing these signals are alternatively named as the Morsi the ME so the C K and the SS pin. 24 00:02:07,740 --> 00:02:17,650 So if you find Morsi missile SDK SS is the same as SDI SD or SC LG and C. 25 00:02:18,000 --> 00:02:26,640 There is also a popular standard called the three wire SBI and a three wire SBI interface bus. 26 00:02:26,730 --> 00:02:37,050 We have the SC l care and the C and only a single pin for data transfer the SBA for way a bus can become 27 00:02:37,170 --> 00:02:38,890 a three way interface. 28 00:02:38,940 --> 00:02:44,280 When D s t i n d S D or data pins are tied together. 29 00:02:45,000 --> 00:02:52,620 However there are some major differences between the standard SBA a four way which we are using in a 30 00:02:52,620 --> 00:02:57,060 three way device in the data transfer protocol. 31 00:02:57,120 --> 00:03:03,870 So for this reason a device must support three way a protocol internally in order to be used as a three 32 00:03:03,870 --> 00:03:05,110 way device. 33 00:03:05,130 --> 00:03:12,050 Many devices support both the SBA for wire and the three way protocol. 34 00:03:12,040 --> 00:03:15,260 Now let's talk about how the SBA works. 35 00:03:15,540 --> 00:03:23,330 So the SBA consist of two shift registers one for the master and the other one for the slave. 36 00:03:23,370 --> 00:03:28,310 Also there is a clock generator in the master side that generates that clock. 37 00:03:28,350 --> 00:03:36,420 For that to shift registers as we can see over here zero hour to pin off the master shift register is 38 00:03:36,420 --> 00:03:44,370 connected to the serial in pin of the slave shift register by the Morsi line and Morsi stands for master 39 00:03:44,370 --> 00:03:52,310 out slave in and the zero in paying off the master shift register is connected to the zero output of 40 00:03:52,320 --> 00:04:01,450 the slave ship to register by the missal line and missile means master in slave out the master clock 41 00:04:01,460 --> 00:04:09,190 generator provides clock to both master and slave shift registers the clock inputs of the shift registers 42 00:04:09,220 --> 00:04:11,430 can be falling or rising. 43 00:04:11,450 --> 00:04:17,530 Age triggered an SBI to shift registers are 8 bits long. 44 00:04:17,950 --> 00:04:25,910 This means that after 8 clock poses the contents of the to shift registers are interchanged. 45 00:04:26,170 --> 00:04:34,060 When the master wants to send a bite of data it places the byte in the shift its places the bytes in 46 00:04:34,060 --> 00:04:42,310 its shift register and generate a clock policies after eight clock policies debate is transmitted to 47 00:04:42,310 --> 00:04:49,330 the slave shift register when the master wants to receive a base of data the slave side should place 48 00:04:49,330 --> 00:04:56,200 the bait in its shift to register and after 8 clock policies that data will be received by the master 49 00:04:56,200 --> 00:04:57,700 shift register. 50 00:04:57,700 --> 00:05:01,330 We shall see how this works programmatically. 51 00:05:01,330 --> 00:05:07,650 Next let's take a look at the SBI clock polarity as we learned earlier in. 52 00:05:07,650 --> 00:05:14,110 You are the communication the transmitter and the receiver must agree on a clock frequency which we 53 00:05:14,110 --> 00:05:16,510 call the bottom rate. 54 00:05:16,570 --> 00:05:23,590 However in SBI communication both master and slave use the same clock. 55 00:05:23,980 --> 00:05:31,990 But the master and slave must agree on the clock polarity and the phase of the clock with respect to 56 00:05:31,990 --> 00:05:43,210 the data C P or L or C pull over here stands for clock polarity and C P H E or C FA stands for the clock 57 00:05:43,210 --> 00:05:52,630 phase at C ball equals zero the ideal value of the clock is zero while at C poorly course one the ideal 58 00:05:52,630 --> 00:06:03,790 value of the clock is one C5 equal 0 means sample data on the leading or 1st clock urge while CFA equals 59 00:06:03,790 --> 00:06:13,180 1 means sample data on the trailing CFA because 0 means sample data on the lead in or first clock edge 60 00:06:13,480 --> 00:06:19,040 while CFA cause 1 means sample data on the trailing or second clock edge. 61 00:06:19,090 --> 00:06:27,070 Also if the ideal value of the clock is zero the lead in or first clock edge is erasing edge but if 62 00:06:27,070 --> 00:06:32,530 the ideal value of the clock is 1 the lead in first the clock edge is a fall edge.